The present invention relates to wafer processing chambers. More particularly, the present invention relates to an apparatus for measuring the DC bias potential of a wafer during plasma processing.
In conventional wafer processing systems, it is common to affix the wafer to the lower electrode pedestal with an electrostatic attraction force provided by an electrostatic chuck (ESC). Electrostatic chucking is commonly implemented by providing a conductive film between two insulation films located on the upper surface of the pedestal. Once a semiconductor wafer is affixed to the ESC, the wafer may be processed.
In the conventional production of semiconductor integrated circuits, plasma is used to promote ionization of a process gas for etching, chemical vapor deposition or sputtering a wafer. In a conventional capacitive plasma processing system, upper and lower electrodes, e.g., large area parallel plates, are provided in a pressure-controlled process chamber with the electrodes facing each other.
In this plasma processing system, the electrode located at the top or upper portion of the chamber, is connected to ground potential, and a high-frequency voltage is applied to the electrode at the bottom or lower portion of the chamber. The lower electrode also serves as a pedestal. A process gas is converted into plasma by the electrical discharge between the upper and lower electrodes.
Strong electric field regions are produced between the electrodes and the plasma. These strong electric field regions are referred to as plasma sheaths. The strong electrical field regions accelerate the electrons and ions from the electrodes to the plasma and vice-versa.
Electrons and ions in the plasma are attracted to a semiconductor wafer residing on the pedestal by the force of an electric field. The ions react with the surface of the semiconductor.
In a conventional plasma processing apparatus, a high-frequency voltage is applied to the lower electrode by a capacitor, and as a result a high-frequency voltage is also applied to the wafer located on the pedestal. This configuration generates a substantially negative DC voltage potential on the pedestal and the wafer. The negative DC voltage potentials are commonly referred to as DC bias potentials.
During the half cycle when the high-frequency voltage is positive, negatively charged electrons in the plasma are attracted to the wafer, whereas during the other half cycle when the high-frequency voltage is negative, positively charged ions in the plasma are attracted to the wafer.
Since an electron has a smaller weight than that of an ion, electrons are more easily transferred to the wafer than the ions are. Consequently, the wafer becomes negatively charged, as more electrons are attracted to the wafer than ions. Thus, the wafer develops a substantially negative DC bias potential.
The DC bias potential increases the energy of the ion presented to the wafer and consequently alters the effectiveness of the wafer processing system. Excessively large bias voltages in the range of 400V to 500V can damage the oxide film on the surface of a wafer. Hence it is crucial in wafer processing systems to be able to monitor and control the DC bias potential of the wafer, or wafer potential. Direct measurement of wafer potential is very difficult. It is virtually impossible to attach or connect a probe to the wafer for direct measurement of the wafer potential, as probes are incapable of withstanding the harsh environment surrounding the wafer.
Several conventional methods have been developed for estimating the wafer potential in a semiconductor processing system. While these conventional methods are capable of providing an estimate of the wafer potential, each method has issues with respect to accuracy, longevity, maintenance, configuration and/or potential for errors.
One convention method for estimating wafer potential uses a probe located within the chamber wall of the plasma processing system. Such a conventional method will now be described with reference to FIG. 1.
FIG. 1 illustrates an example of a conventional wafer processing system 100. As illustrated, wafer processing system 100 includes a communication channel 104, a user interface 106, a 2 MHz RF generator 110, a 27 MHz RF generator 112, a 60 MHz RF generator 114, an impedance matching circuit 116, an ESC 118, an ESC base plate 120, a wafer processing chamber 122, a ceramic coupling ring 126, a hot edge ring (HER) 128, a voltage measuring instrument 130, and a probe 132.
A wafer 102 resides on and is clamped to ESC 118 by an electrostatic attraction force. HER 128 surrounds ESC 118 and provides a uniform etch rate and reduced etch rate drift near the edge of wafer 102. Ceramic coupling ring 126 surrounds ESC 118 and is located beneath HER 128. ESC base plate 120 is located beneath ESC 118 and ceramic coupling ring 126.
Impedance matching circuit 116 receives driving signals from 2 MHz RF generator 110, 27 MHz RF generator 112 and 60 MHz RF generator 114 and provides an appropriate RF signal 124 to ESC base plate 120. Impedance matching circuit 116 is configured such that its impedance is the complex conjugate of the impedance of wafer processing chamber 122, thus minimizing reflected energy and enabling maximum RF energy transfer of the signals provided by 2 MHz RF generator 110, 27 MHz RF generator 112 and 60 MHz RF generator to wafer processing chamber 122.
A plasma 108 is generated above wafer 102 as a result of the RF energy supplied by RF signal 124. Plasma 108 is used to convert or process wafer 102 by bombarding wafer 102 with positively charged ions. A plasma sheath 136 is located between plasma 108 and wafer 102, HER 128. Positively charged ions are propelled across plasma sheath 136 due to a strong electric field region located between plasma 108 and wafer 102, HER 128.
Information related to the status of wafer processing chamber 122 is communicated to user interface 106 by communication channel 104. Further, a user (not shown) is operable to control 2 MHz RF generator 110, 27 MHz RF generator 112 and 60 MHz RF generator 114, by way of user interface 106 and communication channel 136.
Probe 132 is fabricated from electrically conductive material and is attached to the side of wafer processing chamber 122. An electrical conductor 134 is attached to probe 132 and exits wafer processing chamber 122 and connects to voltage measuring instrument 130. Voltage measuring instrument 130 is capable of measuring either AC (peak-to-peak) or DC (bias level) voltages.
Voltage measuring instrument 130 measures the potential of wafer 102.
In conventional wafer processing system 100, probe 132 does not directly contact wafer 102 or plasma sheath 136 and is prone to errors in the measurement of the potential of wafer 102 as presented to voltage measuring instrument 130. Additionally, for configurations of wafer processing system 100 using multi-frequency driven plasma, the errors in the estimated potential for wafer 102 are especially pronounced during complex load transitions. This method for processing wafers can be difficult to calibrate and configure as a result of the complex load transition errors which occur in the estimated potential of wafer 102.
Another conventional method for estimating the wafer potential is by providing electrodes located about the periphery of the ESC, which are in contact with the wafer. The electrodes are commonly constructed of silicon carbide probes. Unfortunately, the use of these electrodes produces contaminants within the process chamber, as the electrodes are erroded by the plasma. This contamination negatively impacts the effectiveness of the plasma by reducing the plasma etch rate. Additionally, the electrodes are consumable and must frequently be replaced requiring significant time, effort and cost.
FIG. 2 illustrates an example of a conventional wafer processing system 200. Wafer processing system 200 contains several common elements wafer processing system 100 of FIG. 1. However, probe 132 and electrical conductor 134 of wafer processing system 100 are replaced with a probe 202 and an electrical conductor 204 in wafer processing system 200. As illustrated in FIG. 2, an upper end of a probe 202 contacts the underside of wafer 102 through a cavity 206 provided through ESC base plate 120, ESC 118 and HER 128. Lower end of probe 202 connects to electrical conductor 204. Electrical conductor 204 connects to voltage measuring instrument 130.
Probe 202 is commonly constructed of a silicon carbide pin. The potential of wafer 102 is detected by probe 202 and transferred to voltage measuring instrument 130. Voltage measuring instrument 130 is then capable of measuring AC (peak-to-peak) or DC (bias level) voltages of wafer 102.
While wafer processing system 200 enables accurate measurement of the potential of wafer 102, it causes contaminants to be projected into the processing chamber from the consumption of probe 202 during wafer processing. These contaminates negatively impact the effectiveness of the plasma by reducing the plasma etch rate. Additionally, the electrodes are consumable and must frequently be replaced requiring significant time, effort and cost.
Another conventional method for measuring the wafer potential is performed by varying the DC voltage applied to the electrostatic chucking electrode and measuring the leakage current between the wafer and the electrostatic chucking electrode. The measured leakage current is then used to estimate the wafer potential.
While the leakage current measurement method for estimating the wafer potential provides a capable wafer processing system, the method is highly dependant upon the magnitude of the leakage current. The magnitude of the leakage current can vary significantly depending upon the configuration of the plasma processing system. Hence, the ESC leakage current detection method for estimating the wafer potential requires considerable time, effort and cost for calibration and configuration.
Unfortunately, conventional methods for measuring the wafer potential are inaccurate, have short lifetimes, are prone to errors and require significant effort for maintenance and configuration. What is needed is a method for measuring the wafer potential that is accurate, has a prolonged lifetime, is not prone to errors and does not require a significant amount of effort for maintenance and configuration.